…1022)

Summary:

The `image_to_nchw` output-staging shader can dispatch one thread per NCHW
output element so writes to the host-visible staging buffer are fully coalesced.
On a discrete GPU the staging buffer is read back over PCIe, where coalescing
writes is a large win: ~11x end-to-end on an RTX 4080 laptop for an ESPCN 2x
super-resolution model.

That output-centric scheme fetches each texel up to 4 times (once per
component). On integrated (mobile / on-die) GPUs the staging buffer is not
PCIe-backed, so write coalescing buys nothing and the redundant fetches are a
net loss: measured +15-42% `image_to_nchw` per-dispatch on Mali-G715 and +3-6%
on Adreno 750.

Gate the two strategies on the physical device type via
`Adapter::is_integrated_gpu()`:
- discrete (not integrated) -> `image_to_nchw_coalesced_*` (output-centric)
- integrated (mobile) -> `image_to_nchw_*` texel-centric (one thread per texel,
  single fetch, contiguous NCHW writes), which is the default.

Gate on device type, NOT `has_unified_memory()`: a discrete GPU with Resizable
BAR exposes a DEVICE_LOCAL | HOST_VISIBLE memory type, so `has_unified_memory()`
returns true for it and would wrongly route it to the slow texel-centric path
(measured ~10x end-to-end regression on an RTX 4080 laptop).

`image_to_nchw.glsl` emits both variants via a `COALESCED_WRITES` codegen flag
(default False). `get_tensor_to_nchw_shader` selects the coalesced variant when
`!is_integrated_gpu()`; the global-workgroup-size picker keys off the shader
name so the dispatch topology matches the chosen variant.

Reviewed By: metascroy

Differential Revision: D112599710